10分鐘看懂IC設計流程 (原創)

IC設計流程大致如下

每個步驟都是必經過程,走完整個過程後輸出一版real chip

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| 定SPEC | --- 決定 Function/clk period/製程liberary ...

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↓

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| 寫RTL / sdc | --- 刻function / 做整合(integration) / insert mbist

|-----------------------| Define clk constraint
↓

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| 驗 Function | --- 跑RTL simulation / 跑Checker (CDC/STA/PA...)

|-----------------------| Design Verification

↓ RTL Level

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| 做 Synthesis | --- 合成netlist 並串DFT (Source files : RTL/sdc)

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↓ Gate Level

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| Check netlist quality | --- check timing (setup) / area / congestion / urate

|-----------------------| run LEC check function equivalent

↓

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| 做 APR | --- Real physical design layout / 長 clk tree /

|-----------------------| 修hold time violation / 長 reset tree

↓

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| Check APR quality | --- Check timing (setup&hold) / area / congestion /

|-----------------------| run LEC / run post-sim / run ptpx / run LVS ...

↓

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| Output mask files |

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↓

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| Tape Out | to TSMC or UMC or Intel ....

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↓ Real chip (Post-silicon)

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| Silicon test | --- ATPG / SLT / Build firmware (driver code)

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投資一定有風險,Post-silicon 有一定的機率轉出石頭,投資前請詳閱公開說明書.