IC設計流程大致如下
每個步驟都是必經過程,走完整個過程後輸出一版real chip
|-----------------------|
| 定SPEC | --- 決定 Function/clk period/製程liberary ...
|-----------------------|
↓
|-----------------------|
| 寫RTL / sdc | --- 刻function / 做整合(integration) / insert mbist
|-----------------------| Define clk constraint
↓
|-----------------------|
| 驗 Function | --- 跑RTL simulation / 跑Checker (CDC/STA/PA...)
|-----------------------| Design Verification
↓ RTL Level
|-----------------------|
| 做 Synthesis | --- 合成netlist 並串DFT (Source files : RTL/sdc)
|-----------------------|
↓ Gate Level
|-----------------------|
| Check netlist quality | --- check timing (setup) / area / congestion / urate
|-----------------------| run LEC check function equivalent
↓
|-----------------------|
| 做 APR | --- Real physical design layout / 長 clk tree /
|-----------------------| 修hold time violation / 長 reset tree
↓
|-----------------------|
| Check APR quality | --- Check timing (setup&hold) / area / congestion /
|-----------------------| run LEC / run post-sim / run ptpx / run LVS ...
↓
|-----------------------|
| Output mask files |
|-----------------------|
↓
|-----------------------|
| Tape Out | to TSMC or UMC or Intel ....
|-----------------------|
↓ Real chip (Post-silicon)
|-----------------------|
| Silicon test | --- ATPG / SLT / Build firmware (driver code)
|-----------------------|
投資一定有風險,Post-silicon 有一定的機率轉出石頭,投資前請詳閱公開說明書.
